NXP Semiconductors freescale K51 Series Reference Manual

ADC Configuration Sample time (ADCK cycles)1 11 1 8The total conversion time depends upon: the sample time (as determined by ADLSMPand ADLSTS bits), the MCU bus frequency, the conversion mode (as determined byMODE and SC1n[DIFF] bits), the high speed configuration (ADHSC bit), and thefrequency of the conversion clock (fADCK).The ADHSC bit is used to configure a higher clock input frequency. This will allowfaster overall conversion times. To meet internal ADC timing requirements, the ADHSCbit adds additional ADCK cycles. Conversions with ADHSC = 1 take two more ADCKcycles. ADHSC should be used when the ADCLK exceeds the limit for ADHSC = 0.After the module becomes active, sampling of the input begins. ADLSMP and ADLSTSselect between sample times based on the conversion mode that is selected. Whensampling is completed, the converter is isolated from the input channel and a successiveapproximation algorithm is performed to determine the digital value of the analog signal.The result of the conversion is transferred to Rn upon completion of the conversionalgorithm.If the bus frequency is less than the fADCK frequency, precise sample time for continuousconversions cannot be guaranteed when short sample is enabled (ADLSMP=0).The maximum total conversion time is determined by the clock source chosen and thedivide ratio selected. The clock source is selectable by the ADICLK bits, and the divideratio is specified by the ADIV bits.The maximum total conversion time for all configurations is summarized in the equationbelow. Refer to the following tables for the variables referenced in the equation.Figure 31-95. Conversion time equationTable 31-107. Single or first continuous time adder (SFCAdder)ADLSMP ADACKEN ADICLK Single or first continuous time adder (SFCAdder)1 x 0x, 10 3 ADCK cycles + 5 bus clock cycles1 1 11 3 ADCK cycles + 5 bus clock cycles11 0 11 5 μs + 3 ADCK cycles + 5 bus clock cycles0 x 0x, 10 5 ADCK cycles + 5 bus clock cycles0 1 11 5 ADCK cycles + 5 bus clock cycles10 0 11 5 μs + 5 ADCK cycles + 5 bus clock cycles1. To achieve this time, ADACKEN must be 1 for at least 5 μs prior to the conversion is initiated.Functional descriptionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011738 Freescale Semiconductor, Inc.