AXBS memory map (continued)Absoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page4000_4600 Priority Registers Slave (AXBS_PRS6) 32 R/W 7654_3210h 17.2.1/3514000_4610 Control Register (AXBS_CRS6) 32 R/W 0000_0000h 17.2.2/3544000_4700 Priority Registers Slave (AXBS_PRS7) 32 R/W 7654_3210h 17.2.1/3514000_4710 Control Register (AXBS_CRS7) 32 R/W 0000_0000h 17.2.2/3544000_4800 Master General Purpose Control Register(AXBS_MGPCR0) 32 R/W 0000_0000h 17.2.3/3564000_4900 Master General Purpose Control Register(AXBS_MGPCR1) 32 R/W 0000_0000h 17.2.3/3564000_4A00 Master General Purpose Control Register(AXBS_MGPCR2) 32 R/W 0000_0000h 17.2.3/3564000_4B00 Master General Purpose Control Register(AXBS_MGPCR3) 32 R/W 0000_0000h 17.2.3/3564000_4C00 Master General Purpose Control Register(AXBS_MGPCR4) 32 R/W 0000_0000h 17.2.3/3564000_4D00 Master General Purpose Control Register(AXBS_MGPCR5) 32 R/W 0000_0000h 17.2.3/3564000_4E00 Master General Purpose Control Register(AXBS_MGPCR6) 32 R/W 0000_0000h 17.2.3/3564000_4F00 Master General Purpose Control Register(AXBS_MGPCR7) 32 R/W 0000_0000h 17.2.3/35617.2.1 Priority Registers Slave (AXBS_PRSn)The priority registers (PRSn) set the priority of each master port on a per slave port basisand reside in each slave port. The priority register can be accessed only with 32-bitaccesses. After the CRSn[RO] bit is set, the PRSn register can only be read; attempts towrite to it have no effect on PRSn and result in a bus-error response to the masterinitiating the write.No two available master ports may be programmed with the same priority level. Attemptsto program two or more masters with the same priority level result in a bus-error responseand the PRSn is not updated.NOTEThe possible values for the PRSn fields depend on the numberof masters available on the device. See the device's ChipConfiguration details for the number of masters supported.Chapter 17 Crossbar Switch (AXBS)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 351