NXP Semiconductors freescale K51 Series Reference Manual

I2Cx_C1 field descriptions (continued)Field Description0 Disabled1 Enabled6IICIEI2C interrupt enableEnables I2C interrupt requests.0 Disabled1 Enabled5MSTMaster mode selectWhen the MST bit is changed from a 0 to a 1, a START signal is generated on the bus and master modeis selected. When this bit changes from a 1 to a 0, a STOP signal is generated and the mode of operationchanges from master to slave.0 Slave mode1 Master mode4TXTransmit mode selectSelects the direction of master and slave transfers. In master mode this bit must be set according to thetype of transfer required. Therefore, for address cycles, this bit is always set. When addressed as a slavethis bit must be set by software according to the SRW bit in the status register.0 Receive1 Transmit3TXAKTransmit acknowledge enableSpecifies the value driven onto the SDA during data acknowledge cycles for both master and slavereceivers. The value of the FACK bit affects NACK/ACK generation.0 An acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK isset) receiving byte.1 No acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK isset) receiving data byte.NOTE: SCL is held low until TXAK is written.2RSTARepeat STARTWriting a one to this bit generates a repeated START condition provided it is the current master. This bitwill always be read as zero. Attempting a repeat at the wrong time results in loss of arbitration.1WUENWakeup enableThe I2C module can wake the MCU from low power mode with no peripheral bus running when slaveaddress matching occurs.0 Normal operation. No interrupt generated when address matching in low power mode.1 Enables the wakeup function in low power mode.0DMAENDMA enableThe DMAEN bit enables or disables the DMA function.Table continues on the next page...Chapter 47 Inter-Integrated Circuit (I2C)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1183