NXP Semiconductors freescale K51 Series Reference Manual

SDHC_XFERTYP field descriptions (continued)Field DescriptionThis bit is set to 1 to indicate that data is present and shall be transferred using the DAT line. It is set to 0for the following:• Commands using only the CMD line (for example: CMD52).• Commands with no data transfer, but using the busy signal on DAT[0] line (R1b or R5b, forexample: CMD38).NOTE: In resume command, this bit shall be set, and other bits in this register shall be set the same aswhen the transfer was initially launched. When the Write Protect switch is on, (i.e. the WPSPL bitis active as ‘0’), any command with a write operation will be ignored. That is to say, when this bitis set, while the DTDSEL bit is 0, writes to the register Transfer Type are ignored.0b No data present1b Data present20CICENCommand Index Check EnableIf this bit is set to 1, the SDHC will check the index field in the response to see if it has the same value asthe command index. If it is not, it is reported as a command index error. If this bit is set to 0, the index fieldis not checked.0b Disable1b Enable19CCCENCommand CRC Check EnableIf this bit is set to 1, the SDHC shall check the CRC field in the response. If an error is detected, it isreported as a Command CRC Error. If this bit is set to 0, the CRC field is not checked. The number of bitschecked by the CRC field value changes according to the length of the response.0b Disable1b Enable18ReservedThis read-only field is reserved and always has the value zero.17–16RSPTYPResponse Type Select00b No response01b Response length 13610b Response length 4811b Response length 48, check busy after response15–6ReservedThis read-only field is reserved and always has the value zero.5MSBSELMulti/Single Block SelectThis bit enables multiple block DAT line data transfers. For any other commands, this bit shall be set to 0.If this bit is 0, it is not necessary to set the block count register.0b Single block1b Multiple blocks4DTDSELData Transfer Direction SelectThis bit defines the direction of DAT line data transfers. The bit is set to 1 by the host driver to transferdata from the SD card to the SDHC and is set to 0 for all other commands.Table continues on the next page...Chapter 49 Secured digital host controller (SDHC)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1315