NXP Semiconductors freescale K51 Series Reference Manual

DMA_INT field descriptions (continued)Field Description0 The interrupt request for corresponding channel is cleared1 The interrupt request for corresponding channel is active10INT10Interrupt Request 100 The interrupt request for corresponding channel is cleared1 The interrupt request for corresponding channel is active9INT9Interrupt Request 90 The interrupt request for corresponding channel is cleared1 The interrupt request for corresponding channel is active8INT8Interrupt Request 80 The interrupt request for corresponding channel is cleared1 The interrupt request for corresponding channel is active7INT7Interrupt Request 70 The interrupt request for corresponding channel is cleared1 The interrupt request for corresponding channel is active6INT6Interrupt Request 60 The interrupt request for corresponding channel is cleared1 The interrupt request for corresponding channel is active5INT5Interrupt Request 50 The interrupt request for corresponding channel is cleared1 The interrupt request for corresponding channel is active4INT4Interrupt Request 40 The interrupt request for corresponding channel is cleared1 The interrupt request for corresponding channel is active3INT3Interrupt Request 30 The interrupt request for corresponding channel is cleared1 The interrupt request for corresponding channel is active2INT2Interrupt Request 20 The interrupt request for corresponding channel is cleared1 The interrupt request for corresponding channel is active1INT1Interrupt Request 10 The interrupt request for corresponding channel is cleared1 The interrupt request for corresponding channel is active0INT0Interrupt Request 00 The interrupt request for corresponding channel is cleared1 The interrupt request for corresponding channel is activeChapter 21 Direct Memory Access Controller (eDMA)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 451