NXP Semiconductors freescale K51 Series Reference Manual

I2Sx_RCCR field descriptions (continued)Field Descriptionused to control the amount of valid data in those 32 bits. In AC97 Mode of operation, if word length is setto any value other than 16 bits, it will result in a word length of 20 bits.0000 Number of Bits/Word: 2; Supported in Implementation: No.0001 Number of Bits/Word: 4; Supported in Implementation: No.0010 Number of Bits/Word: 6; Supported in Implementation: No.0011 Number of Bits/Word: 8; Supported in Implementation: Yes.0100 Number of Bits/Word: 10; Supported in Implementation: Yes.0101 Number of Bits/Word: 12; Supported in Implementation: Yes.0110 Number of Bits/Word: 14; Supported in Implementation: No.0111 Number of Bits/Word: 16; Supported in Implementation: Yes.1000 Number of Bits/Word: 18; Supported in Implementation: Yes.1001 Number of Bits/Word: 20; Supported in Implementation: Yes.1010 Number of Bits/Word: 22; Supported in Implementation: Yes.1011 Number of Bits/Word: 24; Supported in Implementation: Yes.1100 Number of Bits/Word: 26; Supported in Implementation: No.1101 Number of Bits/Word: 28; Supported in Implementation: No.1110 Number of Bits/Word: 30; Supported in Implementation: No.1111 Number of Bits/Word: 32; Supported in Implementation: No.12–8DCFrame Rate Divider Control.These bits are used to control the divide ratio for the programmable frame rate dividers. The divide ratioworks on the word clock. In Normal mode, this ratio determines the word transfer rate. In Network mode,this ratio sets the number of words per frame. The divide ratio ranges from 1 to 32 in Normal mode andfrom 2 to 32 in Network mode. In Normal mode, a divide ratio of 1 (DC=00000) provides continuousperiodic data word transfer. A bit-length frame sync must be used in this case.These bits can be programmed with values ranging from "00000" to "11111" to control the number ofwords in a frame.7–0PMPrescaler Modulus Select.These bits control the prescale divider in the clock generator. This prescaler is used only in Internal Clockmode to divide the internal clock . The bit clock output is available at the clock port. A divide ratio from 1to 256 (PM[7:0] = 0x00 to 0xFF) can be selected.50.3.12 I2S FIFO Control/Status Register (I2Sx_FCSR)The following table indicates the status of the Transmit FIFO Empty flag, with differentsettings of the Transmit FIFO WaterMark bits and varying amounts of data in the TxFIFO.Table 50-40. Status of Transmit FIFO Empty FlagTransmit FIFOWatermark(TFWM)1 2 3 4 5 6 7 8 9 10 11 12 13 14 151 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0Table continues on the next page...Memory map/register definitionK51 Sub-Family Reference Manual, Rev. 6, Nov 20111442 Freescale Semiconductor, Inc.