NXP Semiconductors freescale K51 Series Reference Manual

Table 48-238. UART interrupt sources (continued)Interrupt Source Flag Local enable DMA selectReceiver WT WTWE -Receiver CWT CWTE -Receiver BWT BWTE -Receiver INITD INITDE -Receiver TXT TXTE -Receiver RXT RXTE -Receiver GTV GTVE -48.6.1 RXEDGIF descriptionThe S2[RXEDGIF] is set when an active edge is detected on the RxD pin. Hence, theactive edge can only be detected when in two wire mode. A RXEDGIF interrupt is onlygenerated when S2[RXEDGIF] is set. If RXEDGIE is not enabled prior toS2[RXEDGIF] getting set, an interrupt is not generated until S2[RXEDGIF] bit gets set.48.6.1.1 RxD edge detect sensitivityEdge sensitivity can be software programmed to be either falling or rising. The polarityof the edge sensitivity is selected using the S2[RXINV] bit. To detect falling edgeS2[RXINV] is programmed to zero and to detect rising edge S2[RXINV] is programmedto one.Synchronizing logic is used prior to detect edges. Prior to detecting an edge, the receivedata on RxD input must be at the de-asserted logic level. A falling edge is detected whenthe RxD input signal is seen as a logic 1 (the deasserted level) during one module clockcycle and then a logic 0 (the asserted level) during the next cycle. A rising edge isdetected when the input is seen as a logic 0 during one module clock cycle and then alogic 1 during the next cycle.48.6.1.2 Clearing RXEDGIF interrupt requestWriting a logic 1 to the S2[RXEDGIF] bit immediately clears the RXEDGIF interruptrequest even if the RxD input remains asserted. S2[RXEDGIF] will remain set if anotheractive edge is detected on RxD while attempting to clear the S2[RXEDGIF] flag bywriting a 1 to it.System level interrupt sourcesK51 Sub-Family Reference Manual, Rev. 6, Nov 20111292 Freescale Semiconductor, Inc.