NXP Semiconductors freescale K51 Series Reference Manual

• External DMA mode:• For a read operation, when there are more words received in the buffer than theamount set in the RDWML register, a DMA request is sent out to inform theexternal DMA to fetch the data. The request will be immediately de-assertedwhen there is an access on the DATPORT register. If the number of words in thebuffer after the current burst meets or exceeds RDWML value, then the DMArequest is asserted again. So for instance if there are twice as many words in thebuffer than the RDWML value, there are two successive DMA requests withonly one cycle of de-assertion between. The write operation is similar.Note the accesses CPU polling mode and external DMA mode both use the IPbus, and if the external DMA is enable, in both modes an external DMA requestis sent out whenever the buffer is ready.• Internal DMA mode (includes simple and advanced DMA access's):• The internal DMA access, either by simple or advanced DMA, is over thecrossbar switch bus. For internal DMA access mode, the external DMA requestwill never be sent out.For a read operation, when there are more words in the buffer than the amount set in theWML register, the internal DMA starts fetching data over the crossbar switch bus. ExceptINCR4 and INCR8, the burst type is always INCR mode and the burst length depends onthe shortest of following factors:1. Burst length configured in the burst length field of the WML register2. Watermark level boundary3. Block size boundary4. Data boundary configured in the current descriptor (if the ADMA is active)5. 1 KB address boundaryWrite operation is similar.Sequential and contiguous access is necessary to ensure the pointer address value iscorrect. Random or skipped access is not possible. The byte order, by reset, is littleendian mode. The actually byte order is swapped inside the buffer, according to theendian mode configured by software, as illustrated in the following diagrams. For a hostwrite operation, byte order is swapped after data is fetched from the buffer and ready tosend to the SD bus. For a host read operation, byte order is swapped before the data isstored into the buffer.Chapter 49 Secured digital host controller (SDHC)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1357