NXP Semiconductors freescale K51 Series Reference Manual

46.4.2.4.1 Filling the TX FIFOHost software or other intelligent blocks can add (push) entries to the TX FIFO bywriting to the PUSHR. When the TX FIFO is not full, the TX FIFO Fill Flag (TFFF) inthe SR is set. The TFFF bit is cleared when TX FIFO is full and the DMA controllerindicates that a write to PUSHR is complete. Writing a '1' to the TFFF bit also clears it.The TFFF can generate a DMA request or an interrupt request. See Transmit FIFO FillInterrupt or DMA Request for details.The DSPI ignores attempts to push data to a full TX FIFO, the state of the TX FIFO doesnot change and no error condition is indicated.46.4.2.4.2 Draining the TX FIFOThe TX FIFO entries are removed (drained) by shifting SPI data out through the shiftregister. Entries are transferred from the TX FIFO to the shift register and shifted out aslong as there are valid entries in the TX FIFO. Every time an entry is transferred from theTX FIFO to the shift register, the TX FIFO Counter decrements by one. At the end of atransfer, the TCF bit in the SR is set to indicate the completion of a transfer. The TXFIFO is flushed by writing a '1' to the CLR_TXF bit in MCR.If an external bus master initiates a transfer with a DSPI slave while the slave's DSPI TXFIFO is empty, the Transmit FIFO Underflow Flag (TFUF) in the slave's SR is set. SeeTransmit FIFO Underflow Interrupt Request for details.46.4.2.5 Receive First In First Out (RX FIFO) Buffering MechanismThe RX FIFO functions as a buffer for data received on the SIN pin. The RX FIFO holds4 received SPI data frames. The number of entries in the RX FIFO is device-specific. SPIdata is added to the RX FIFO at the completion of a transfer when the received data in theshift register is transferred into the RX FIFO. SPI data are removed (popped) from theRX FIFO by reading the DSPI POP RX FIFO Register (POPR). RX FIFO entries canonly be removed from the RX FIFO by reading the POPR or by flushing the RX FIFO.The RX FIFO Counter field (RXCTR) in the DSPI Status Register (SR) indicates thenumber of valid entries in the RX FIFO. The RXCTR is updated every time the POPR isread or SPI data is copied from the shift register to the RX FIFO.The POPNXTPTR field in the SR points to the RX FIFO entry that is returned when thePOPR is read. The POPNXTPTR contains the positive offset from RXFR0 in number of32-bit registers. For example, POPNXTPTR equal to two means that the RXFR2 containsthe received SPI data that will be returned when POPR is read. The POPNXTPTR field isChapter 46 SPI (DSPI)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1155