NXP Semiconductors freescale K51 Series Reference Manual

I2Sx_TX1 field descriptions (continued)Field DescriptionExample: If Tx FIFO0 is in use and you write Data1 - 16 to TX0, Data16 does not overwrite Data1. Data1 -15 are stored in the FIFO while Data16 is discarded. Example: If Tx FIFO0 is not in use and you writeData1, Data2 to TX0, then Data2 does not overwrite Data1 and is discarded.NOTE: Enable I2S (CR[I2SEN]=1) before writing to the I2S transmit data registers.50.3.3 I2S Receive Data Registers 0 (I2Sx_RX0)The RX0 registers store the data received by the I2S.Addresses: I2S0_RX0 is 4002_F000h base + 8h offset = 4002_F008hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RRX0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0I2Sx_RX0 field descriptionsField Description31–0RX0I2S Receive DataThese bits store the data received by the I2S. These are implemented as the first word of their respectiveRx FIFOs. These bits receive data from the RXSR depending on the mode of operation. In case bothFIFOs are in use, data is transferred to each data register alternately. RX1 can only be used in two-channel mode of operation.50.3.4 I2S Receive Data Registers 1 (I2Sx_RX1)The RX1 registers store the data received by the I2S.Addresses: I2S0_RX1 is 4002_F000h base + Ch offset = 4002_F00ChBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RRX1WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0I2Sx_RX1 field descriptionsField Description31–0RX1I2S Receive DataThese bits store the data received by the I2S. These are implemented as the first word of their respectiveRx FIFOs. These bits receive data from the RXSR depending on the mode of operation. In case bothMemory map/register definitionK51 Sub-Family Reference Manual, Rev. 6, Nov 20111422 Freescale Semiconductor, Inc.