NXP Semiconductors freescale K51 Series Reference Manual

SDHC_PRSSTAT field descriptions (continued)Field DescriptionThis status bit is generated if either the DLA or the RTA is set to 1. If this bit is 0, it indicates that theSDHC can issue the next SD/MMC Command. Commands with a busy signal belong to CDIHB (e.g. R1b,R5b type). Except in the case when the command busy is finished, changing from 1 to 0 generates atransfer complete interrupt in the interrupt status register.NOTE: The SD host driver can save registers for a suspend transaction after this bit has changed from 1to 0.0b Can issue command which uses the DAT line1b Cannot issue command which uses the DAT line0CIHBCommand Inhibit (CMD)If this status bit is 0, it indicates that the CMD line is not in use and the SDHC can issue a SD/MMCCommand using the CMD line.This bit is set also immediately after the transfer type register is written. This bit is cleared when thecommand response is received. Even if the CDIHB bit is set to 1, Commands using only the CMD line canbe issued if this bit is 0. Changing from 1 to 0 generates a command complete interrupt in the interruptstatus register. If the SDHC cannot issue the command because of a command conflict error (Refer tocommand CRC error) or because of a command not issued by auto CMD12 error, this bit will remain 1and the command complete is not set. The status of issuing an auto CMD12 does not show on this bit.0b Can issue command using only CMD line1b Cannot issue command49.4.11 Protocol Control Register (SDHC_PROCTL)There are three cases to restart the transfer after stop at the block gap. Which case isappropriate depends on whether the SDHC issues a suspend command or the SD cardaccepts the suspend command.1. If the host driver does not issue a suspend command, the continue request shall beused to restart the transfer.2. If the host driver issues a suspend command and the SD card accepts it, a resumecommand shall be used to restart the transfer.3. If the host driver issues a suspend command and the SD card does not accept it, thecontinue request shall be used to restart the transfer.Any time stop at block gap request stops the data transfer, the host driver shall wait for atransfer complete (in the interrupt status register), before attempting to restart the transfer.When restarting the data transfer by continue request, the host driver shall clear the stopat block gap request before or simultaneously.Memory map and register definitionK51 Sub-Family Reference Manual, Rev. 6, Nov 20111324 Freescale Semiconductor, Inc.