NXP Semiconductors freescale K51 Series Reference Manual

NOTEWhen queuing a break character, it will be transmittedfollowing the completion of the data value currently beingshifted out from the shift register. This means that if data isqueued in the data buffer to be transmitted, the break characterwill preempt that queued data. The queued data will then betransmitted after the break character is complete.48.4.1.5 Idle charactersAn idle character contains all logic 1s and has no start, stop, or parity bit. Idle characterlength depends on the C1[M] and C1[PE] bits and the C4[M10] bit. The preamble is asynchronizing idle character that begins the first transmission initiated after setting theC2[TE] bit. When C7816[ISO_7816E] is set/enabled, idle characters are not sent ordetected. When data is not being transmitted the data I/O line is in an inactive state.If the C2[TE] bit is cleared during a transmission, the transmit data output signalbecomes idle after completion of the transmission in progress. Clearing and then settingthe C2[TE] bit during a transmission queues an idle character to be sent after thedataword currently being transmitted.NoteWhen queuing an idle character the idle character will betransmitted following the completion of the data value currentlybeing shifted out from the shift register. This means that if datais queued in the data buffer to be transmitted, the idle characterwill preempt that queued data. The queued data will then betransmitted after the idle character is complete.If the C2[TE] bit is cleared and the transmission is completed,the UART is not the master of the TXD pin.48.4.1.6 Hardware flow controlThe transmitter supports hardware flow control by gating the transmission with the valueof CTS. If the clear-to-send operation is enabled, the character is transmitted when CTSis asserted. If CTS is deasserted in the middle of a transmission with characters remainingin the receiver data buffer, the character in the shift register is sent and TXD remains inthe mark state until CTS is reasserted.Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1263