NXP Semiconductors freescale K51 Series Reference Manual

LCD_FDSR field descriptionsField Description31–16ReservedReservedThis read-only field is reserved and always has the value zero.15FDCFFault detection complete flagFDCF indicates that the fault detection is completed. Writing 1 to this bit clears this bit to zero. This bitalso acts as an interrupt flag when FDCIEN is set. Software can use either interrupt or polling to check ifone pin fault detection is completed.0 Fault detection is not completed.1 Fault detection is completed.14–8ReservedReservedThis read-only field is reserved and always has the value zero.7–0FDCNTFault detect counterContains how many “one/high” are sampled inside the fault detect sample window.0 No "one" samples.1 1 "one" samples.2 2 "one" samples....254 254 "one" samples.255 255 or more "one" samples. The FDCNT can overflow. Therefore, FDSWW and FDPRS must bereconfigured for proper sampling.53.3.5 LCD pin enable register (LCD_PENn)When LCDEN = 1, each PEN bit enables the corresponding LCD pin (LCD_Pn) for LCDoperation.Initialize these registers before enabling the LCD controller.NOTEThe reset value of this register depends on the reset type:• POR -- 0x0000_0000Addresses: LCD_PENL is 400B_E000h base + 10h offset = 400B_E010hLCD_PENH is 400B_E000h base + 14h offset = 400B_E014hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RPENWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Chapter 53 LCD Controller (SLCD)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1537