NXP Semiconductors freescale K51 Series Reference Manual

Table 10-32. SDHC Signal Descriptions (continued)Chip signal name Module signalnameDescription I/OSDHC0_D1 SDHC_D1 8-bit mode: DAT1 line4-bit mode: DAT1 line or interrupt detect1-bit mode: Interrupt detectI/OSDHC0_D2 SDHC_D2 4-/8-bit mode: DAT2 line or read wait1-bit mode: Read waitI/OSDHC0_D3 SDHC_D3 4-/8-bit mode: DAT3 line or configured as card detection pin1-bit mode: May be configured as card detection pinI/OTable 10-33. I2S 0 Signal DescriptionsChip signal name Module signalnameDescription I/OI2S0_MCLK — Serial master clock output I/OI2S0_RX_BCLK SRCK Serial receive clock. SRCK can be used as an input or output.• In asynchronous mode the receiver uses this clock signaland it is always continuous.• In synchronous mode, the STCK port is used instead forclocking in data.I/OI2S0_RX_FS SRFS Serial receive frame Sync. The SRFS port can be used as an inputor output. The frame sync is used by the receiver to synchronizethe transfer of data. The frame sync signal can be one bit or oneword in length and can occur one bit before the transfer of data orright at the transfer of data. If SRFS is configured as an input, theexternal device should drive SRFS during the rising edge of STCKor SRCK.I/OI2S0_RXD SRXD Serial receive data. The SRXD port is an input and is used to bringserial data into the receive data shift register.II2S0_TX_BCLK STCK Serial transmit clock. The STCK port can be used as an input oroutput. This clock signal is used by the transmitter and can becontinuous or gated. During gated clock mode, data on STCK isvalid only during the transmission of data. Otherwise, it is pulled tothe inactive state. In synchronous mode, this port is used by thetransmit and receive sections.I/OI2S0_TX_FS STFS Serial transmit frame sync. The STFS port can be used as an inputor output. The frame sync is used by the transmitter to synchronizethe transfer of data. The frame sync signal can be one bit or oneword in length and can occur one bit before the transfer of data orright at the transfer of data. In synchronous mode, this port is usedby both the transmit and receive sections. In gated clock mode,frame sync signals are not used. If STFS is configured as an input,the external device should drive STFS during the rising edge ofSTCK if TSCKP is positive-edge triggered. The external deviceshould drive STFS during the falling edge of STCK if TSCKP isnegative-edge triggered.I/OTable continues on the next page...Chapter 10 Signal Multiplexing and Signal DescriptionsK51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 235