NXP Semiconductors freescale K51 Series Reference Manual

SPI memory map (continued)Absoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page4002_C084 DSPI Receive FIFO Registers (SPI0_RXFR2) 32 R 0000_0000h 46.3.11/11504002_C088 DSPI Receive FIFO Registers (SPI0_RXFR3) 32 R 0000_0000h 46.3.11/11504002_D000 DSPI Module Configuration Register (SPI1_MCR) 32 R/W 0000_4001h 46.3.1/11334002_D008 DSPI Transfer Count Register (SPI1_TCR) 32 R/W 0000_0000h 46.3.2/11364002_D00C DSPI Clock and Transfer Attributes Register (In MasterMode) (SPI1_CTAR0) 32 R/W 7800_0000h 46.3.3/11364002_D00C DSPI Clock and Transfer Attributes Register (In SlaveMode) (SPI1_CTAR0_SLAVE) 32 R/W 7800_0000h 46.3.4/11414002_D010 DSPI Clock and Transfer Attributes Register (In MasterMode) (SPI1_CTAR1) 32 R/W 7800_0000h 46.3.3/11364002_D02C DSPI Status Register (SPI1_SR) 32 R/W See section 46.3.5/11424002_D030 DSPI DMA/Interrupt Request Select and Enable Register(SPI1_RSER) 32 R/W 0000_0000h 46.3.6/11454002_D034 DSPI PUSH TX FIFO Register In Master Mode(SPI1_PUSHR) 32 R/W 0000_0000h 46.3.7/11474002_D034 DSPI PUSH TX FIFO Register In Slave Mode(SPI1_PUSHR_SLAVE) 32 R/W 0000_0000h 46.3.8/11494002_D038 DSPI POP RX FIFO Register (SPI1_POPR) 32 R 0000_0000h 46.3.9/11494002_D03C DSPI Transmit FIFO Registers (SPI1_TXFR0) 32 R 0000_0000h 46.3.10/11504002_D040 DSPI Transmit FIFO Registers (SPI1_TXFR1) 32 R 0000_0000h 46.3.10/11504002_D044 DSPI Transmit FIFO Registers (SPI1_TXFR2) 32 R 0000_0000h 46.3.10/11504002_D048 DSPI Transmit FIFO Registers (SPI1_TXFR3) 32 R 0000_0000h 46.3.10/11504002_D07C DSPI Receive FIFO Registers (SPI1_RXFR0) 32 R 0000_0000h 46.3.11/11504002_D080 DSPI Receive FIFO Registers (SPI1_RXFR1) 32 R 0000_0000h 46.3.11/11504002_D084 DSPI Receive FIFO Registers (SPI1_RXFR2) 32 R 0000_0000h 46.3.11/11504002_D088 DSPI Receive FIFO Registers (SPI1_RXFR3) 32 R 0000_0000h 46.3.11/1150Chapter 46 SPI (DSPI)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1131