NXP Semiconductors freescale K51 Series Reference Manual

DMA memory map (continued)Absoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page4000_9178 TCD Last Destination Address Adjustment/Scatter GatherAddress (DMA_TCD11_DLASTSGA) 32 R/W Undefined 21.3.28/4654000_917C TCD Control and Status (DMA_TCD11_CSR) 16 R/W Undefined 21.3.29/4664000_917ETCD Beginning Minor Loop Link, Major Loop Count(Channel Linking Enabled)(DMA_TCD11_BITER_ELINKYES)16 R/W Undefined 21.3.30/4684000_917ETCD Beginning Minor Loop Link, Major Loop Count(Channel Linking Disabled)(DMA_TCD11_BITER_ELINKNO)16 R/W Undefined 21.3.31/4694000_9180 TCD Source Address (DMA_TCD12_SADDR) 32 R/W Undefined 21.3.17/4574000_9184 TCD Signed Source Address Offset (DMA_TCD12_SOFF) 16 R/W Undefined 21.3.18/4584000_9186 TCD Transfer Attributes (DMA_TCD12_ATTR) 16 R/W Undefined 21.3.19/4584000_9188 TCD Minor Byte Count (Minor Loop Disabled)(DMA_TCD12_NBYTES_MLNO) 32 R/W Undefined 21.3.20/4594000_9188 TCD Signed Minor Loop Offset (Minor Loop Enabled andOffset Disabled) (DMA_TCD12_NBYTES_MLOFFNO) 32 R/W Undefined 21.3.21/4604000_9188 TCD Signed Minor Loop Offset (Minor Loop and OffsetEnabled) (DMA_TCD12_NBYTES_MLOFFYES) 32 R/W Undefined 21.3.22/4614000_918C TCD Last Source Address Adjustment(DMA_TCD12_SLAST) 32 R/W Undefined 21.3.23/4624000_9190 TCD Destination Address (DMA_TCD12_DADDR) 32 R/W Undefined 21.3.24/4624000_9194 TCD Signed Destination Address Offset(DMA_TCD12_DOFF) 16 R/W Undefined 21.3.25/4634000_9196 TCD Current Minor Loop Link, Major Loop Count (ChannelLinking Enabled) (DMA_TCD12_CITER_ELINKYES) 16 R/W Undefined 21.3.26/4634000_9196 DMA_TCD12_CITER_ELINKNO 16 R/W Undefined 21.3.27/4644000_9198 TCD Last Destination Address Adjustment/Scatter GatherAddress (DMA_TCD12_DLASTSGA) 32 R/W Undefined 21.3.28/4654000_919C TCD Control and Status (DMA_TCD12_CSR) 16 R/W Undefined 21.3.29/4664000_919ETCD Beginning Minor Loop Link, Major Loop Count(Channel Linking Enabled)(DMA_TCD12_BITER_ELINKYES)16 R/W Undefined 21.3.30/4684000_919ETCD Beginning Minor Loop Link, Major Loop Count(Channel Linking Disabled)(DMA_TCD12_BITER_ELINKNO)16 R/W Undefined 21.3.31/469Table continues on the next page...Chapter 21 Direct Memory Access Controller (eDMA)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 431