NXP Semiconductors freescale K51 Series Reference Manual

38.3.10 Features Mode Selection (FTMx_MODE)This register contains the control bits used to configure the fault interrupt and faultcontrol, capture test mode, PWM synchronization, write protection, channel outputinitialization, and enable the enhanced features of the FTM. These controls relate to allchannels within this module.Addresses: FTM0_MODE is 4003_8000h base + 54h offset = 4003_8054hFTM1_MODE is 4003_9000h base + 54h offset = 4003_9054hFTM2_MODE is 400B_8000h base + 54h offset = 400B_8054hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0FAULTIEFAULTMCAPTESTPWMSYNCWPDISINITFTMENWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0FTMx_MODE field descriptionsField Description31–8ReservedThis read-only field is reserved and always has the value zero.7FAULTIEFault Interrupt EnableEnables the generation of an interrupt when a fault is detected by FTM and the FTM fault control isenabled.0 Fault control interrupt is disabled.1 Fault control interrupt is enabled.6–5FAULTMFault Control ModeDefines the FTM fault control mode.This field is write protected. It can be written only when MODE[WPDIS] = 1.00 Fault control is disabled for all channels.01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode isthe manual fault clearing.10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing.11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.Table continues on the next page...Memory Map and Register DefinitionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011874 Freescale Semiconductor, Inc.