NXP Semiconductors freescale K51 Series Reference Manual

• These masters have write access to a portion of bank 1 when FlexNVM is used withFlexRAM as EEPROM.• For bank 0 and bank 1:• Prefetch support for data and instructions is enabled for crossbar masters 0, 1, 2.• The cache is configured for least recently used (LRU) replacement for all fourways.• The cache is configured for data or instruction replacement.• The single-entry buffer is enabled.Though the default configuration provides a high degree of flash acceleration, advancedusers may desire to customize the FMC buffer configurations to maximize throughput fortheir use cases. When reconfiguring the FMC for custom use cases, do not program theFMC's control registers while the flash memory or FlexMemory is being accessed.Instead, change the control registers with a routine executing from RAM in supervisormode.The FMC's cache and buffering controls within PFB0CR and PFB1CR allow the tuningof resources to suit particular applications' needs. The cache and two buffers are eachcontrolled individually. The register controls enable buffering and prefetching permemory bank and access type (instruction fetch or data reference). The cache alsosupports three types of LRU replacement algorithms:• LRU per set across all four ways,• LRU with ways [0-1] for instruction fetches and ways [2-3] for data fetches, and• LRU with ways [0-2] for instruction fetches and way [3] for data fetches.As an application example: if both instruction fetches and data references are accessingbank 0, control is available to send instruction fetches, data references, or both to thecache or the single-entry buffer. Likewise, speculation can be enabled or disabled foreither type of access. If both instruction fetches and data references are cached, thecache's way resources may be divided in several ways between the instruction fetches anddata references.In another application example, the cache can be configured for replacement from bank0, while the single-entry buffer can be enabled for bank 1 only. This configuration isideal for applications that use bank 0 for program space and bank 1 for data space.Chapter 27 Flash Memory Controller (FMC)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 605