The crossbar terminates all master IDLE transfers, as opposed to allowing the terminationto come from one of the slave busses. Additionally, when no master is requesting accessto a slave port, the crossbar drives IDLE transfers onto the slave bus, even though adefault master may be granted access to the slave port.When a slave bus is being idled by the crossbar, it can park the slave port on the masterport indicated by CRSn[PARK]. This is done to save the initial clock of arbitration delaythat otherwise would be seen if the master had to arbitrate to gain control of the slaveport. The slave port can also be put into Low Power Park mode to save power, by usingCRSn[PCTL].17.3.2 Register coherencyBecause the content of the registers has a real-time effect on the operation of the crossbar,it is important to understand that any register modifications take effect as soon as theregister is written. The values of the registers do not track with slave-port-related masteraccesses, but instead track only with slave accesses.The MGPCRx[AULB] bits are the exception to this rule. The update of these bits is onlyrecognized when the master on that master port runs an IDLE cycle, even though theslave bus cycle to write them will have already terminated successfully. If theMGPCRx[AULB] bits are written between two burst accesses, the new AULB encodingsdo not take effect until an IDLE cycle is initiated by the master on that master port.17.3.3 ArbitrationThe crossbar switch supports two arbitration schemes:• A fixed-priority comparison algorithm• A round-robin fairness algorithmThe arbitration scheme is independently programmable for each slave port.17.3.3.1 Arbitration during undefined length burstsArbitration points during an undefined length burst are defined by the current master'sMGPCR[AULB] field setting. When a defined length is imposed on the burst via theAULB bits, the undefined length burst is treated as a single or series of single back-to-back fixed-length burst accesses.The following figure illustrates an example:Functional DescriptionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011358 Freescale Semiconductor, Inc.