NXP Semiconductors freescale K51 Series Reference Manual

LCD_GCR field descriptions (continued)Field DescriptionFor CPSEL = 1 • Adjust the clock source for the charge pump.• Higher loads require higher charge pumpclock rates.00 — Fastest clock source for charge pump (LCDglass capacitance 8000 pF or lower).01 — Intermediate clock source for charge pump(LCD glass capacitance 6000 pF or lower).10 — Intermediate clock source for charge pump(LCD glass capacitance 4000 pF or lower).11 — Slowest clock source for charge pump (LCDglass capacitance 2000 pF or lower).19ReservedReservedThis read-only field is reserved and always has the value zero.18ReservedReservedThis field is reserved.17–16VSUPPLYVoltage supply controlConfigures whether the LCD controller power supply is external or internal. Avoid modifying this bit fieldwhile the LCD controller is enabled (for example, LCDEN = 1).00 Drive VLL2 internally from VDD.01 Drive VLL3 internally from VDD.10 Reserved11 Drive VLL3 externally from VDD or drive VLL1 internally from VIREG.15LCDIENLCD frame frequency interrupt enableEnables an LCD interrupt event that coincides with the LCD controller frame frequency.0 No interrupt request is generated by this event.1 When LCDIF bit is set, this event causes an interrupt request.14FDCIENLCD fault detection complete interrupt enableEnables an LCD interrupt event when fault detection is completed.0 No interrupt request is generated by this event.1 When a fault is detected and FDCF bit is set, this event causes an interrupt request.13–12ALTDIVLCD alternate clock dividerThis bit is used as a clock divider to divide the alternate clock before it is selected as LCD clock source.0 Divide factor = 1 (No divide)1 Divide factor = 82 Divide factor = 643 Divide factor = 512Table continues on the next page...Chapter 53 LCD Controller (SLCD)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1531