NXP Semiconductors freescale K51 Series Reference Manual

SIM_CLKDIV1 field descriptions (continued)Field Description15–0ReservedThis read-only field is reserved and always has the value zero.12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)Address: SIM_CLKDIV2 is 4004_7000h base + 1048h offset = 4004_8048hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16RI2SDIV0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RI2SFRAC0USBDIVUSBFRACWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SIM_CLKDIV2 field descriptionsField Description31–20I2SDIVI2S clock divider valueThis field sets the divide value for when the fractional clock divider is used as the source for the I2Smaster clock. The clock input to the fractional clock divider is set by the SOPT2[I2SSRC] bit.Divider output clock = Divider input clock × [(I2SFRAC+1) / (I2SDIV+1) ]NOTE: The I2S clock must be disabled (SCGC6[I2S] = 0) before altering this bitfield.19–16ReservedThis read-only field is reserved and always has the value zero.15–8I2SFRACI2S clock divider fractionThis field sets the multiply value for when the fractional clock divider is used as a the source for I2Smaster clock. The clock input to the fractional clock divider is set by the SOPT2[I2SSRC] bit.Divider output clock = Divider input clock × [(I2SFRAC+1) / (I2SDIV+1) ]NOTE: The I2S clock must be disabled (SCGC6[I2S] = 0) before altering this bitfield.7–4ReservedThis read-only field is reserved and always has the value zero.3–1USBDIVUSB clock divider divisorThis field sets the divide value for the fractional clock divider when the MCGFLLCLK/MCGPLLCLK clockis the USB clock source (SOPT2[USBSRC] = 1).Table continues on the next page...Chapter 12 System integration module (SIM)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 283