NXP Semiconductors freescale K51 Series Reference Manual

1. Bus clock.2. SDHC clock.3. System clock.The module monitors the activities of all other modules, supplies the clocks for them, andwhen enabled, automatically gates off the corresponding clocks.49.5.5 Clock generatorThe clock generator generates the SDHC_CLK by peripheral source clock in two stages.The following diagram illustrates the structure of the divider. The term "base" representsthe frequency of peripheral source clock.1st divisorby 1, 2, 3, ..., 16Base (SD_CLK_2X*)SD_CLK2nd divisorby (1*), 2, 4, ..., 256DIVFigure 49-35. Two stages of the clock dividerThe first stage outputs an intermediate clock (DIV), which can be base, base/2, base/3, ...,or base/16.The second stage is a prescaler, and outputs the actual clock (SDHC_CLK). This clock isthe driving clock for all sub modules of the SD protocol unit, and the sync FIFOs tosynchronize with the data rate from the internal data buffer. The frequency of the clockoutput from this stage, can be DIV, DIV/2, DIV/4,..., or DIV/256. Thus the highestfrequency of the SDHC_CLK is base, and the next highest is base/2, while the lowestfrequency is base/4096. If the base clock is of equal duty ratio (usually true), the dutycycle of SDHC_CLK is also 50%, even when the compound divisor is an odd value.49.5.6 SDIO card interruptThis section discusses SDIO interrupt handling.49.5.6.1 Interrupts in 1-bit modeIn this case the DAT[1] pin is dedicated to providing the interrupt function. An interruptis asserted by pulling the DAT[1] low from the SDIO card, until the interrupt service isfinished to clear the interrupt.Chapter 49 Secured digital host controller (SDHC)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1371