NXP Semiconductors freescale K51 Series Reference Manual

38.4.12 InvertingThe invert functionality swaps the signals between channel (n) and channel (n+1)outputs. The inverting operation is selected when (FTMEN = 1), (QUADEN = 0),(DECAPEN = 0), (COMBINE = 1), (COMP = 1), (CPWMS = 0), and (INVm = 1),where m represents a channel pair. The INVm bit in INVCTRL register is updated withits buffer value according to INVCTRL Register SynchronizationIn high-true (ELSnB:ELSnA = 1:0) combine mode, the channel (n) output is forced lowat the beginning of the period (FTM counter = CNTIN), forced high at the channel (n)match and forced low at the channel (n+1) match. If the inverting is selected, the channel(n) output behavior is changed to force high at the beginning of the PWM period, forcelow at the channel (n) match and force high at the channel (n+1) match. See the followingfigure.NOTEchannel (n+1) matchFTM counterchannel (n) matchchannel (n+1) outputbefore the invertingwrite 1 to INV(m) bitINV(m) bit bufferINVCTRL registersynchronizationINV(m) bitchannel (n) outputafter the invertingchannel (n+1) outputafter the invertingINV(m) bit selects the inverting to the pair channels (n) and (n+1).channel (n) outputbefore the invertingFigure 38-225. Channels (n) and (n+1) Outputs After the Inverting in High-True(ELSnB:ELSnA = 1:0) Combine ModeNote that the ELSnB:ELSnA bits value should be consider since that they define theactive state of the channels outputs. In low-true (ELSnB:ELSnA = X:1) combine mode,the channel (n) output is forced high at the beginning of the period, forced low at thechannel (n) match and forced high at the channel (n+1) match. In the case the inverting isselected the channels (n) and (n+1) present waveforms as shown in the following figure.Chapter 38 FlexTimer (FTM)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 949