NXP Semiconductors freescale K51 Series Reference Manual

2. Set the control level to 2 via zero-bit scans3. Execute the Store Format (STFMT) command (00011) to set the scan format registerto 1149.7 scan format9.3 Debug Port Pin DescriptionsThe debug port pins default after POR to their JTAG functionality with the exception ofJTAG_TRST_b and can be later reassigned to their alternate functionalities. In cJTAGand SWD modes JTAG_TDI and JTAG_TRST_b can be configured to alternate GPIOfunctions.Table 9-2. Debug port pinsPin Name JTAG Debug Port cJTAG Debug Port SWD Debug Port Internal Pull-up\DownType Description Type Description Type DescriptionJTAG_TMS/SWD_DIOI/O JTAG TestModeSelectionI/O cJTAG Data I/O Serial WireDataPull-upJTAG_TCLK/SWD_CLKI JTAG TestClockI cJTAG Clock I Serial WireClockPull-downJTAG_TDI I JTAG TestData Input- - - - Pull-upJTAG_TDO/TRACE_SWOO JTAG TestData OutputO Trace outputover a singlepinO Trace outputover a singlepinN/CJTAG_TRST_bI JTAG Reset I cJTAG Reset - - Pull-up9.4 System TAP connectionThe system JTAG controller is connected in parallel to the ARM TAP controller. Thesystem JTAG controller IR codes overlay the ARM JTAG controller IR codes withoutconflict. Refer to the IR codes table for a list of the available IR codes. The output of theTAPs (TDO) are muxed based on the IR code which is selected. This design is fullyJTAG compliant and appears to the JTAG chain as a single TAP. At power on reset,ARM's IDCODE (IR=4'b1110) is selected.Chapter 9 DebugK51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 207