NXP Semiconductors freescale K51 Series Reference Manual

ADCx_SC2 field descriptions (continued)Field Description00 Default voltage reference pin pair (external pins VREFH and VREFL)01 Alternate reference pair (VALTH and VALTL). This pair may be additional external pins or internalsources depending on MCU configuration. Consult the Chip Configuration information for detailsspecific to this MCU.10 Reserved11 Reserved31.3.7 Status and control register 3 (ADCx_SC3)The SC3 register controls the calibration, continuous convert, and hardware averagingfunctions of the ADC module.Addresses: ADC0_SC3 is 4003_B000h base + 24h offset = 4003_B024hADC1_SC3 is 400B_B000h base + 24h offset = 400B_B024hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0CALCALF 0ADCOAVGEAVGSWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0ADCx_SC3 field descriptionsField Description31–8ReservedThis read-only field is reserved and always has the value zero.7CALCalibrationCAL begins the calibration sequence when set. This bit stays set while the calibration is in progress and iscleared when the calibration sequence is completed. The CALF bit must be checked to determine theresult of the calibration sequence. Once started, the calibration routine cannot be interrupted by writes tothe ADC registers or the results will be invalid and the CALF bit will set. Setting the CAL bit will abort anycurrent conversion.6CALFCalibration failed flagCALF displays the result of the calibration sequence. The calibration sequence will fail if ADTRG = 1, anyADC register is written, or any stop mode is entered before the calibration sequence completes. TheCALF bit is cleared by writing a 1 to this bit.Table continues on the next page...Register DefinitionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011720 Freescale Semiconductor, Inc.