NXP Semiconductors freescale K51 Series Reference Manual

PDB memory mapAbsoluteaddress(hex)Register name Width(in bits) Access Reset value Section/page4003_6000 Status and Control Register (PDB0_SC) 32 R/W 0000_0000h 37.3.1/8354003_6004 Modulus Register (PDB0_MOD) 32 R/W 0000_FFFFh 37.3.2/8374003_6008 Counter Register (PDB0_CNT) 32 R 0000_0000h 37.3.3/8384003_600C Interrupt Delay Register (PDB0_IDLY) 32 R/W 0000_FFFFh 37.3.4/8384003_6010 Channel n Control Register 1 (PDB0_CH0C1) 32 R/W 0000_0000h 37.3.5/8394003_6014 Channel n Status Register (PDB0_CH0S) 32 w1c 0000_0000h 37.3.6/8404003_6018 Channel n Delay 0 Register (PDB0_CH0DLY0) 32 R/W 0000_0000h 37.3.7/8414003_601C Channel n Delay 1 Register (PDB0_CH0DLY1) 32 R/W 0000_0000h 37.3.8/8414003_6038 Channel n Control Register 1 (PDB0_CH1C1) 32 R/W 0000_0000h 37.3.5/8394003_603C Channel n Status Register (PDB0_CH1S) 32 w1c 0000_0000h 37.3.6/8404003_6040 Channel n Delay 0 Register (PDB0_CH1DLY0) 32 R/W 0000_0000h 37.3.7/8414003_6044 Channel n Delay 1 Register (PDB0_CH1DLY1) 32 R/W 0000_0000h 37.3.8/8414003_6150 DAC Interval Trigger n Control Register (PDB0_DACINTC0) 32 R/W 0000_0000h 37.3.9/8424003_6154 DAC Interval n Register (PDB0_DACINT0) 32 R/W 0000_0000h 37.3.10/8424003_6158 DAC Interval Trigger n Control Register (PDB0_DACINTC1) 32 R/W 0000_0000h 37.3.9/8424003_615C DAC Interval n Register (PDB0_DACINT1) 32 R/W 0000_0000h 37.3.10/8424003_6190 Pulse-Out n Enable Register (PDB0_POEN) 32 R/W 0000_0000h 37.3.11/8434003_6194 Pulse-Out n Delay Register (PDB0_PO0DLY) 32 R/W 0000_0000h 37.3.12/843Memory Map and Register DefinitionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011834 Freescale Semiconductor, Inc.