NXP Semiconductors freescale K51 Series Reference Manual

UARTx_CFIFO field descriptions (continued)Field Description0 RXUF flag does not generate an interrupt to the host.1 RXUF flag generates an interrupt to the host.48.3.18 UART FIFO Status Register (UARTx_SFIFO)This register provides various status information regarding the transmit and receiverbuffers/FIFOs, including interrupt information. This register may be written or read atanytime.Addresses: UART0_SFIFO is 4006_A000h base + 12h offset = 4006_A012hUART1_SFIFO is 4006_B000h base + 12h offset = 4006_B012hUART2_SFIFO is 4006_C000h base + 12h offset = 4006_C012hUART3_SFIFO is 4006_D000h base + 12h offset = 4006_D012hUART4_SFIFO is 400E_A000h base + 12h offset = 400E_A012hUART5_SFIFO is 400E_B000h base + 12h offset = 400E_B012hBit 7 6 5 4 3 2 1 0Read TXEMPT RXEMPT 0 TXOF RXUFWriteReset 1 1 0 0 0 0 0 0UARTx_SFIFO field descriptionsField Description7TXEMPTTransmit Buffer/FIFO EmptyThis status bit asserts when there is no data in the Transmit FIFO/buffer. This bit does not take intoaccount data that is in the transmit shift register.0 Transmit buffer is not empty.1 Transmit buffer is empty.6RXEMPTReceive Buffer/FIFO EmptyThis status bit asserts when there is no data in the receive FIFO/Buffer. This bit does not take intoaccount data that is in the receive shift register.0 Receive buffer is not empty.1 Receive buffer is empty.5–2ReservedThis read-only field is reserved and always has the value zero.1TXOFTransmitter Buffer Overflow FlagThis flag indicates that more data has been written to the transmit buffer than it can hold. This bit willassert regardless of the value of CFIFO[TXOFE]. However, an interrupt will only be issued to the host ifthe CFIFO[TXOFE] bit is set. This flag is cleared by writing a "1".Table continues on the next page...Memory map and registersK51 Sub-Family Reference Manual, Rev. 6, Nov 20111246 Freescale Semiconductor, Inc.