49.7.1 Initialization activeThe driver cannot set SYSCTL[INITA] bit when any of the command line or data lines isactive, so the driver must ensure both PRSSTAT[CDIHB] and PRSSTAT[CIHB] bits arecleared. And in order to auto clear the SYSCTL[INITA] bit, the SYSCTL[SDCLKEN]bit must be '1', otherwise no clocks can go out to the card and SYSCTL[INITA] willnever clear.49.7.2 Software polling procedureFor polling read or write, once the software begins a buffer read or write, it must accessexactly the number of times as the values set in the watermark level register; moreover, ifthe block size is not the times of the value in watermark level register (read and writerespectively), the software must access exactly the remained number of words at the endof each block. For example, for read operation, if the WML[RDWML] is 4, indicating thewatermark level is 16 bytes, block size is 40 bytes, and the block number is 2, then theaccess times for the burst sequence in the whole transfer process must be 4, 4, 2, 4, 4, 2.49.7.3 Suspend operationIn order to suspend the data transfer, the software must inform SDHC that the suspendcommand is successfully accepted. To achieve this, after the Suspend command isaccepted by the SDIO card, software must send another normal command marked assuspend command (XFERTYP[CMDTYP] bits set as '01') to inform SDHC that thetransfer is suspended.If software needs resume the suspended transfer, it should read the value inBLKATTR[BLKCNT] to save the remained number of blocks before sending the normalcommand marked as suspend, otherwise on sending such 'suspend' command, SDHC willregard the current transfer is aborted and change BLKATTR[BLKCNT] to its originalvalue, instead of keeping the remained number of blocks.49.7.4 Data length settingFor either ADMA (ADMA1 or ADMA2) transfer, the data in the data buffer must beword aligned, so the data length set in the descriptor must be times of 4.Software restrictionsK51 Sub-Family Reference Manual, Rev. 6, Nov 20111408 Freescale Semiconductor, Inc.