NXP Semiconductors freescale K51 Series Reference Manual

Table 49-36. Format of the ADMA2 descriptor table (continued)Valid Valid = 1 indicates this line of descriptor is effective. If valid = 0 generate ADMA error interrupt andstop ADMA.End End = 1 indicates current descriptor is the ending one.Int Int = 1 generates DMA interrupt when this descriptor is done.System Address Register points tothe head node of Descriptor TableSystem Address RegisterAdvanced DMASystem MemoryAddressAddress3AttributeTran, EndAddress Length AttributeTranLinkLength1Length2Address1Address2Data Length (invisible)Data Address (invisible)FlagsStateMachineSDMAADMA ErrorPage DataDescriptor TablePage DataTransfer CompleteDMA InterruptFigure 49-33. Concept and access method of ADMA2 descriptor table49.5.2.4.2 ADMA interruptIf the 'interrupt' flag of descriptor is set, ADMA will generate an interrupt according todifferent type descriptor:For ADMA1:• Set type descriptor: interrupt is generated when data length is set.• Tran type descriptor: interrupt is generated when this transfer is complete.• Link type descriptor: interrupt is generated when new descriptor address is set.• Nop type descriptor: interrupt is generated just after this descriptor is fetched.For ADMA2:• Tran type descriptor: interrupt is generated when this transfer is complete.• Link type descriptor: interrupt is generated when new descriptor address is set.• Nop/Rsv type descriptor: interrupt is generated just after fetch this descriptor.Chapter 49 Secured digital host controller (SDHC)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1367