Clock name DescriptionBus clock MCGOUTCLK divided by OUTDIV2 clocks the bus slavesand peripheral (excluding memories)Flash clock MCGOUTCLK divided by OUTDIV4 clocks the flash memoryMCGIRCLK MCG output of the slow or fast internal reference clockMCGFFCLK MCG output of the slow internal reference clock or a dividedMCG external reference clock. The MCGFFCLK is furtherdivided by 2 before being made available to modules outsidethe MCG (as shown in the preceding figure).MCGOUTCLK MCG output of either IRC, MCGFLLCLK, MCGPLLCLK, orMCG's external reference clock that sources the core,system, bus, and flash clock. It is also an option for thedebug trace clock.MCGFLLCLK MCG output of the FLL. MCGFLLCLK or MCGPLLCLK mayclock some modules.MCGPLLCLK MCG output of the PLL. MCGFLLCLK or MCGPLLCLK mayclock some modules.MCG external reference clock Input clock to the MCG sourced by the system oscillator(OSCCLK) or RTC oscillatorOSCCLK System oscillator output of the internal oscillator or sourceddirectly from EXTALOSCERCLK System oscillator output sourced from OSCCLKthat mayclock some on-chip modulesOSC32KCLK System oscillator 32kHz outputERCLK32K Clock source for some modules that is chosen asOSC32KCLK or the RTC clockRTC clock RTC oscillator output for the RTC moduleLPO PMC 1kHz output5.4.1 Device clock summaryThe following table provides more information regarding the on-chip clocks.Table 5-1. Clock SummaryClock name Run modeclock frequencyVLPR modeclock frequencyClock source Clock is disabledwhen…MCGOUTCLK Up to 100 MHz Up to 2 MHz MCG In all stop modesCore clock Up to 100 MHz Up to 2 MHz MCGOUTCLK clockdividerIn all wait and stopmodesSystem clock Up to 100 MHz Up to 2 MHz MCGOUTCLK clockdividerIn all stop modesBus clock Up to 50 MHz Up to 2 MHz MCGOUTCLK clockdividerIn all stop modesFlash clock Up to 25 MHz Up to 1 MHz MCGOUTCLK clockdividerIn all stop modesTable continues on the next page...Chapter 5 Clock DistributionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 171