NXP Semiconductors freescale K51 Series Reference Manual

Section Number Title Page50.3.19 I2S AC97 Channel Status Register (I2Sx_ACCST).....................................................................................145250.3.20 I2S AC97 Channel Enable Register (I2Sx_ACCEN)...................................................................................145250.3.21 I2S AC97 Channel Disable Register (I2Sx_ACCDIS).................................................................................145350.4 Functional description...................................................................................................................................................145350.4.1 Detailed operating mode descriptions..........................................................................................................145350.4.2 I2S clocking.................................................................................................................................................146950.4.3 External frame and clock operation.............................................................................................................147450.4.4 Receive interrupt enable bit description.......................................................................................................147650.4.5 Transmit interrupt enable bit description.....................................................................................................147750.4.6 Internal frame and clock shutdown..............................................................................................................147850.4.7 Reset.............................................................................................................................................................147950.5 Initialization/application information...........................................................................................................................1479Chapter 51General purpose input/output (GPIO)51.1 Introduction...................................................................................................................................................................148351.1.1 Features........................................................................................................................................................148351.1.2 Modes of operation......................................................................................................................................148351.1.3 GPIO signal descriptions.............................................................................................................................148451.2 Memory map and register definition.............................................................................................................................148551.2.1 Port Data Output Register (GPIOx_PDOR).................................................................................................148851.2.2 Port Set Output Register (GPIOx_PSOR)....................................................................................................148851.2.3 Port Clear Output Register (GPIOx_PCOR)................................................................................................148951.2.4 Port Toggle Output Register (GPIOx_PTOR).............................................................................................148951.2.5 Port Data Input Register (GPIOx_PDIR).....................................................................................................149051.2.6 Port Data Direction Register (GPIOx_PDDR).............................................................................................149051.3 Functional description...................................................................................................................................................149151.3.1 General purpose input..................................................................................................................................149151.3.2 General purpose output................................................................................................................................1491K51 Sub-Family Reference Manual, Rev. 6, Nov 201148 Freescale Semiconductor, Inc.