NXP Semiconductors freescale K51 Series Reference Manual

AXBS_MGPCRn field descriptions (continued)Field Description101 Reserved110 Reserved111 Reserved17.3 Functional Description17.3.1 General operationWhen a master accesses the crossbar switch the access is immediately taken. If thetargeted slave port of the access is available, then the access is immediately presented onthe slave port. It is possible to make single-clock, or zero wait state, accesses through thecrossbar. If the targeted slave port of the access is busy or parked on a different masterport, the requesting master simply sees wait states inserted until the targeted slave portcan service the master's request. The latency in servicing the request depends on eachmaster's priority level and the responding peripheral's access time.Because the crossbar switch appears to be just another slave to the master device, themaster device has no knowledge of whether it actually owns the slave port it is targeting.While the master does not have control of the slave port it is targeting, it simply waits.A master is given control of the targeted slave port only after a previous access to adifferent slave port completes, regardless of its priority on the newly targeted slave port.This prevents deadlock from occurring when:• A higher priority master has:• An outstanding request to one slave port that has a long response time and• A pending access to a different slave port, and• A lower priority master is also making a request to the same slave port as the pendingaccess of the higher priority master.After the master has control of the slave port it is targeting, the master remains in controlof that slave port until it gives up the slave port by running an IDLE cycle or by leavingthat slave port for its next access.The master could also lose control of the slave port if another higher priority mastermakes a request to the slave port; however, if the master is running a fixed-length bursttransfer it retains control of the slave port until that transfer completes. Based onMGPCR[AULB], the master either retains control of the slave port when doing undefinedlength incrementing burst transfers or loses the bus to a higher priority master.Chapter 17 Crossbar Switch (AXBS)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 357