NXP Semiconductors freescale K51 Series Reference Manual

It is important to note that these DAP control and status registers are not memory mappedwithin the system memory map and are only accessible via the Debug Access Port (DAP)using JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 withthe available registers shown in the table below.Table 9-4. MDM-AP Register SummaryAddress Register Description0x0100_0000 Status See MDM-AP Status Register0x0100_0004 Control See MDM-AP Control Register0x0100_00FC ID Read-only identification register thatalways reads as 0x001C_0000SWJ-DPSELECT[31:24] (APSEL) selects the APSELECT[7:4] (APBANKSEL) selects the bankA[3:2] from the APACC selects the registerwithin the bankAHB Access Port(AHB-AP) MDM-APStatus 0x00Control 0x01IDR 0x3F AHB-APSELECT[31:24] = 0x00 selects the AHB-APSee ARM documentation for further detailsMDM-APSELECT[31:24] = 0x01 selects the MDM-APSELECT[7:4] = 0x0 selects the bank with Status and CtrlA[3:2] = 2’b00 selects the Status RegisterA[3:2] = 2’b01 selects the Control RegisterSELECT[7:4] = 0xF selects the bank with IDRA[3:2] = 2’b11 selects the IDR Register(IDR register reads 0x001C_0000)Bus MatrixSee Control and Status RegisterDescriptionsDebug PortInternal BusAccess PortData[31:0] A[7:4] A[3:2] RnWAPSELDecode Debug Port ID Register (DPIDR)Control/Status (CTRL/STAT)AP Select (SELECT)Read Buffer (REBUFF)DP Registers0x000x040x080x0CData[31:0] A[3:2] RnWDPACCData[31:0] A[3:2] RnWAPACCDebug Port(DP)GenericSee the ARM Debug Interface v5p1 Supplement.Figure 9-3. MDM AP AddressingChapter 9 DebugK51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 209