NXP Semiconductors freescale K51 Series Reference Manual

54.3 Register descriptionThis section provides a detailed description of the JTAGC block registers accessiblethrough the TAP interface, including data registers and the instruction register. Individualbit-level descriptions and reset states of each register are included. These registers are notmemory-mapped and can only be accessed through the TAP.54.3.1 Instruction registerThe JTAGC block uses a 4-bit instruction register as shown in the following figure. Theinstruction register allows instructions to be loaded into the block to select the test to beperformed or the test data register to be accessed or both. Instructions are shifted inthrough TDI while the TAP controller is in the Shift-IR state, and latched on the fallingedge of TCK in the Update-IR state. The latched instruction value can only be changed inthe Update-IR and Test-Logic-Reset TAP controller states. Synchronous entry into theTest-Logic-Reset state results in the IDCODE instruction being loaded on the fallingedge of TCK. Asynchronous entry into the Test-Logic-Reset state results in asynchronousloading of the IDCODE instruction. During the Capture-IR TAP controller state, theinstruction shift register is loaded with the value 0001b , making this value the register'sread value when the TAP controller is sequenced into the Shift-IR state.RWReset:Instruction Code2 1 00 0 0 10 0 0 13Figure 54-2. Instruction register54.3.2 Bypass registerThe bypass register is a single-bit shift register path selected for serial data transferbetween TDI and TDO when the BYPASS, CLAMP, HIGHZ or reserve instructions areactive. After entry into the Capture-DR state, the single-bit shift register is set to a logic0. Therefore, the first bit shifted out after selecting the bypass register is always a logic 0.Chapter 54 JTAG Controller (JTAGC)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1593