NXP Semiconductors freescale K51 Series Reference Manual

49.4.18 Watermark Level Register (SDHC_WML)Both write and read watermark levels (FIFO threshold) are configurable. There value canrange from 1 to 128 words. Both write and read burst lengths are also configurable. Therevalue can range from 1 to 31 words.Address: SDHC_WML is 400B_1000h base + 44h offset = 400B_1044hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 0 WRWML 0 0 RDWMLWReset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0SDHC_WML field descriptionsField Description31–29ReservedThis read-only field is reserved and always has the value zero.28–24ReservedThis read-only field is reserved and always has the value zero.23–16WRWMLWrite Watermark LevelThe number of words used as the watermark level (FIFO threshold) in a DMA write operation. Also thenumber of words as a sequence of write bursts in back-to-back mode. The maximum legal value for thewrite watermark level is 128.15–13ReservedThis read-only field is reserved and always has the value zero.12–8ReservedThis read-only field is reserved and always has the value zero.7–0RDWMLRead Watermark LevelThe number of words used as the watermark level (FIFO threshold) in a DMA read operation. Also thenumber of words as a sequence of read bursts in back-to-back mode. The maximum legal value for theread water mark level is 128.49.4.19 Force Event Register (SDHC_FEVT)The force event register is not a physically implemented register. Rather, it is an addressat which the interrupt status register can be written if the corresponding bit of theinterrupt status enable register is set. This register is a write only register and writing 0 toit has no effect. Writing 1 to this register actually sets the corresponding bit of interruptstatus register. A read from this register always results in 0's. In order to change thecorresponding status bits in the interrupt status register, make sure to setSYSCTL[IPGEN] so that bus clock is always active.Chapter 49 Secured digital host controller (SDHC)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1347