21.3.14 Error Register (DMA_ERR)The ERR provides a bit map for the 16 channels, signaling the presence of an error foreach channel. The eDMA engine signals the occurrence of an error condition by settingthe appropriate bit in this register. The outputs of this register are enabled by the contentsof the EEI, and then routed to the interrupt controller. During the execution of theinterrupt-service routine associated with any DMA errors, it is software’s responsibilityto clear the appropriate bit, negating the error-interrupt request. Typically, a write to theCERR in the interrupt-service routine is used for this purpose. The normal DMA channelcompletion indicators (setting the transfer control descriptor DONE flag and the possibleassertion of an interrupt request) are not affected when an error is detected.The contents of this register can also be polled because a non-zero value indicates thepresence of a channel error regardless of the state of the EEI. The state of any givenchannel’s error indicators is affected by writes to this register; it is also affected by writesto the CERR. On writes to the ERR, a one in any bit position clears the correspondingchannel’s error status. A zero in any bit position has no affect on the correspondingchannel’s current error status. The CERR is provided so the error indicator for a singlechannel can easily be cleared.Address: DMA_ERR is 4000_8000h base + 2Ch offset = 4000_802ChBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0RERR15ERR14ERR13ERR12ERR11ERR10ERR9ERR8ERR7ERR6ERR5ERR4ERR3ERR2ERR1ERR0W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1cReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DMA_ERR field descriptionsField Description31–16ReservedThis read-only field is reserved and always has the value zero.Table continues on the next page...Memory map/register definitionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011452 Freescale Semiconductor, Inc.