NXP Semiconductors freescale K51 Series Reference Manual

CMPx_FPR field descriptionsField Description7–0FILT_PERFilter Sample PeriodWhen CR1[SE] is equal to zero, this field specifies the sampling period, in bus clock cycles, of thecomparator output filter. Setting FILT_PER to 0x0 disables the filter. Filter programming and latencydetails appear in the Functional Description.This field has no effect when CR1[SE] is equal to one. In that case, the external SAMPLE signal is usedto determine the sampling period.32.7.4 CMP Status and Control Register (CMPx_SCR)Addresses: CMP0_SCR is 4007_3000h base + 3h offset = 4007_3003hCMP1_SCR is 4007_3008h base + 3h offset = 4007_300BhCMP2_SCR is 4007_3010h base + 3h offset = 4007_3013hBit 7 6 5 4 3 2 1 0Read 0 DMAEN SMELB IER IEF CFR CFF COUTWrite w1c w1cReset 0 0 0 0 0 0 0 0CMPx_SCR field descriptionsField Description7ReservedThis read-only field is reserved and always has the value zero.6DMAENDMA Enable ControlThe DMAEN bit enables the DMA transfer triggered from the CMP module. When this bit is set, a DMArequest is asserted when the CFR or CFF bit is set.0 DMA disabled.1 DMA enabled.5SMELBStop Mode Edge/Level Interrupt ControlThis bit controls whether the CFR and CFF bits are edge sensitive or level sensitive in Stop mode.NOTE: This bit should always be programmed to 0 to keep the comparator working and to wake up theMCU.0 CFR/CFF are level sensitive in Stop mode. CFR will be asserted when COUT is high. CFF will beasserted when COUT is low.1 CFR/CFF are edge sensitive in Stop mode. An active low-to-high transition must be seen on COUT toassert CFR, and an active high-to-low transition must be seen on COUT to assert CFF.4IERComparator Interrupt Enable RisingThe IER bit enables the CFR interrupt from the CMP. When this bit is set, an interrupt will be assertedwhen the CFR bit is set.Table continues on the next page...Memory Map/Register DefinitionsK51 Sub-Family Reference Manual, Rev. 6, Nov 2011768 Freescale Semiconductor, Inc.