NXP Semiconductors freescale K51 Series Reference Manual

The eDMA design supports the following hardware service request sequence:Table 21-293. Hardware service request process, cycles 1–7Cycle Description1 eDMA peripheral request is asserted.2 The eDMA peripheral request is registered locally in theeDMA module and qualified. TCDn_CSR[START] bit initiatedrequests start at this point with the registering of the userwrite to TCDn word 7.3 Channel arbitration begins.4 Channel arbitration completes. The transfer control descriptorlocal memory read is initiated.5–6 The first two parts of the activated channel's TCD is readfrom the local memory. The memory width to the eDMAengine is 64 bits, so the entire descriptor can be accessed infour cycles.7 The first system bus read cycle is initiated, as the third part ofthe channel's TCD is read from the local memory. Dependingon the state of the crossbar switch, arbitration at the systembus may insert an additional cycle of delay here.The exact timing from this point is a function of the response times for the channel's readand write accesses. In the case of an internal peripheral bus read and internal SRAMwrite, the combined data phase time is 4 cycles. For an SRAM read and internalperipheral bus write, it is 5 cycles.Table 21-294. Hardware service request process, cycles 8–17Cycle DescriptionWith internal peripheralbus read and internalSRAM writeWith SRAM read andinternal peripheral buswrite8–11 8–12 The last part of the TCD is read in. This cycle represents thefirst data phase for the read, and the address phase for thedestination write.12 13 This cycle represents the data phase of the last destinationwrite.13 14 The eDMA engine completes the execution of the inner minorloop and prepares to write back the required TCDn fields intothe local memory. The TCDn word 7 is read and checked forchannel linking or scatter/gather requests.14 15 The appropriate fields in the first part of the TCDn are writtenback into the local memory.15 16 The fields in the second part of the TCDn are written backinto the local memory. This cycle coincides with the nextchannel arbitration cycle start.Table continues on the next page...Chapter 21 Direct Memory Access Controller (eDMA)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 477