NXP Semiconductors freescale K51 Series Reference Manual

SDHC_XFERTYP field descriptions (continued)Field Description0b Write (host to card)1b Read (card to host)3ReservedThis read-only field is reserved and always has the value zero.2AC12ENAuto CMD12 EnableMultiple block transfers for memory require a CMD12 to stop the transaction. When this bit is set to 1, theSDHC will issue a CMD12 automatically when the last block transfer has completed. The host driver shallnot set this bit to issue commands that do not require CMD12 to stop a multiple block data transfer. Inparticular, secure commands defined in File Security Specification (see reference list) do not requireCMD12. In single block transfer, the SDHC will ignore this bit no matter if it is set or not.0b Disable1b Enable1BCENBlock Count EnableThis bit is used to enable the Block Count register, which is only relevant for multiple block transfers.When this bit is 0, the internal counter for block is disabled, which is useful in executing an infinitetransfer.0b Disable1b Enable0DMAENDMA EnableThis bit enables DMA functionality. If this bit is set to 1, a DMA operation shall begin when the host driversets the DPSEL bit of this register. Whether the simple DMA, or the advanced DMA, is active depends onthe PROCTL[DMAS].0b Disable1b Enable49.4.5 Command Response 0 (SDHC_CMDRSP0)This register is used to store part 0 of the response bits from the card.Address: SDHC_CMDRSP0 is 400B_1000h base + 10h offset = 400B_1010hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R CMDRSP0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SDHC_CMDRSP0 field descriptionsField Description31–0CMDRSP0Command Response 0Memory map and register definitionK51 Sub-Family Reference Manual, Rev. 6, Nov 20111316 Freescale Semiconductor, Inc.