NXP Semiconductors freescale K51 Series Reference Manual

38.3.21 Quadrature Decoder Control and Status (FTMx_QDCTRL)This register has the control and status bits for the quadrature decoder mode.Addresses: FTM0_QDCTRL is 4003_8000h base + 80h offset = 4003_8080hFTM1_QDCTRL is 4003_9000h base + 80h offset = 4003_9080hFTM2_QDCTRL is 400B_8000h base + 80h offset = 400B_8080hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16R 0WReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0PHAFLTRENPHBFLTRENPHAPOLPHBPOLQUADMODEQUADIRTOFDIRQUADENWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FTMx_QDCTRL field descriptionsField Description31–8ReservedThis read-only field is reserved and always has the value zero.7PHAFLTRENPhase A Input Filter EnableEnables the filter for the quadrature decoder phase A input. The filter value for the phase A input isdefined by the CH0FVAL field of FILTER. The phase A filter is also disabled when CH0FVAL is zero.0 Phase A input filter is disabled.1 Phase A input filter is enabled.6PHBFLTRENPhase B Input Filter EnableEnables the filter for the quadrature decoder phase B input. The filter value for the phase B input isdefined by the CH1FVAL field of FILTER. The phase B filter is also disabled when CH1FVAL is zero.0 Phase B input filter is disabled.1 Phase B input filter is enabled.5PHAPOLPhase A Input PolaritySelects the polarity for the quadrature decoder phase A input.Table continues on the next page...Chapter 38 FlexTimer (FTM)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 897