NXP Semiconductors freescale K51 Series Reference Manual

PDBx_CHnC1 field descriptions (continued)Field DescriptionThese bits enable the PDB ADC pre-trigger outputs. Only lower M pre-trigger bits are implemented in thisMCU.0 PDB channel's corresponding pre-trigger disabled.1 PDB channel's corresponding pre-trigger enabled.37.3.6 Channel n Status Register (PDBx_CHS)Addresses: PDB0_CH0S is 4003_6000h base + 14h offset = 4003_6014hPDB0_CH1S is 4003_6000h base + 3Ch offset = 4003_603ChBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0 CF 0 ERRWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PDBx_CHnS field descriptionsField Description31–24ReservedThis read-only field is reserved and always has the value zero.23–16CFPDB Channel FlagsThe CF[m] bit is set when the PDB counter matches the CHnDLYm. Write 0 to clear these bits.15–8ReservedThis read-only field is reserved and always has the value zero.7–0ERRPDB Channel Sequence Error FlagsOnly the lower M bits are implemented in this MCU.0 Sequence error not detected on PDB channel's corresponding pre-trigger.1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggeredfor a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered byone of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel'scorresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1’s to clear thesequence error flags.Memory Map and Register DefinitionK51 Sub-Family Reference Manual, Rev. 6, Nov 2011840 Freescale Semiconductor, Inc.