NXP Semiconductors freescale K51 Series Reference Manual

49.6.3.4 ADMA usageTo use the ADMA in a data transfer, the host driver must prepare the correct descriptorchain prior to sending the read/write command. The steps to accomplish this are:1. Create a descriptor to set the data length that the current descriptor group is about totransfer. The data length should be even numbers of the block size.2. Create another descriptor to transfer the data from the address setting in thisdescriptor. The data address must be at a page boundary (4 KB address aligned).3. If necessary, create a link descriptor containing the address of the next descriptor.The descriptor group is created in steps 1 ~ 3.4. Repeat steps 1 ~ 3 until all descriptors are created.5. In the last descriptor, set the end flag to 1 and make sure the total length of alldescriptors match the product of the block size and block number configured in theBLKATTR register.6. Set the DSADDR register to the address of the first descriptor and set thePROCTL[DMAS] field to 01 to select the ADMA.7. Issue a write or read command with the XFERTYP[DMAEN] bit set to 1.Steps 1 ~ 5 are independent of step 6, so step 6 can finish before steps 1 ~ 5. Regardingthe descriptor configuration, it is recommended not to use the link descriptor as itrequires extra system memory access.49.6.3.5 Transfer errorThis section discusses the handling of transfer errors.49.6.3.5.1 CRC errorIt is possible at the end of a block transfer, that a write CRC status error or read CRCerror occurs. For this type of error the latest block received shall be discarded. This isbecause the integrity of the data block is not guaranteed. It is recommended to discard thefollowing data blocks and re-transfer the block from the corrupted one. For a multi-blocktransfer, the host driver shall issue a CMD12 to abort the current process and start thetransfer by a new data command. In this scenario, even when the XFERTYP[AC12EN]and BCEND bits are set, the SDHC does not automatically send a CMD12 because theChapter 49 Secured digital host controller (SDHC)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1391