NXP Semiconductors freescale K51 Series Reference Manual

b. If the TDRE flag is set, or there is space in the transmit buffer, write the data tobe transmitted to (C3[T8]/D). A new transmission will not result until data existsin the transmit buffer.3. Repeat step 2 for each subsequent transmission.NoteDuring normal operation, the S1[TDRE] flag is set when theshift register is loaded with the next data to be transmitted fromthe transmit buffer and the number of datawords contained inthe transmit buffer is less than or equal to the value inTWFIFO[TXWATER], which occurs 9/16ths of a bit time afterthe start of the stop bit of the previous frame.To separate messages with preambles with minimum idle line time, use this sequencebetween messages:1. Write the last dataword of the first message to C3[T8]/D.2. Wait for the S1[TDRE] flag to go high (with TWFIFO[TXWATER] = 0), indicatingthe transfer of the last frame to the transmit shift register.3. Queue a preamble by clearing and then setting the C2[TE] bit.4. Write the first (and subsequent) datawords of the second message to C3[T8]/D.48.8.4 Overrun (OR) flag implicationsTo be flexible the overrun flag (OR) operates slight differently depending on the mode ofoperation. As such there may be implications that need to be carefully considered. Thissection clarifies that behavior and the resulting implications. Regardless of mode, if adataword is received while the S1[OR] flag is set, the S1[RDRF] and S1[IDLE] flags areblocked from asserting. If the S1[RDRF] or S1[IDLE] flag were previously asserted theywill remain asserted until cleared.48.8.4.1 Overrun operationThe assertion of the S1[OR] flag indicates that a significant event has occurred. Theassertion indicates that received data has been lost since there was a lack of room to storeit in the data buffer. Hence, while the S1[OR] flag is set no further data will be stored inthe data buffer until the S1[OR] flag is cleared. This ensures that the application will beable to handle the overrun condition.Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1297