NXP Semiconductors freescale K51 Series Reference Manual

Table 50-51. I2S bit clock and frame rate as a function of PSR, PM, and DIV2 (continued)Bits/wordWords/frameMCLK/network clockfreq (MHz)TCCR Bit clock(kHz)STCKFramerate(kHz)DIV2 PSR PM WL DC16 1 11.2896 0 0 7 7 0 705.6 44.116 2 11.2896 0 0 3 7 1 1411.2 44.116 4 11.2896 0 0 1 7 3 2822.4 44.1The table below shows an example of programming clock controller divider ratios togenerate the appropriate oversampling clock and peripheral clock frequencies for varioussampling rates. In these examples, the master mode is selected either by setting I2Smaster bit (CR[I2SMODE] = 01b) or individually programming the I2S in network,synchronous, transmit internal mode. (The table specifically illustrates the I2S modefrequencies/sample rates). The oversampling clock is network clock.I2S master mode requires a 32-bit word length, regardless of the actual data type.Consequently, the fixed I2S frame rate of 64 bits per frame (word length (TCCR[WL])can be any value) and TCCR[DC] = 1 are assumed.Table 50-52. I2S system clock, bit clock, frame clock in master modeSampling/framerate (kHz)Over- samplingrateMCLK/networkclockfreq (MHz)TCCR Bit clk (kHz)STCKDIV2 PSR PM44.10 384 16.934 0 0 2 2822.3322.05 384 16.934 0 0 5 1411.1711.025 384 16.934 0 0 11 705.5848.00 256 12.288 0 0 1 307250.4.3 External frame and clock operationWhen applying external frame sync and clock signals to I2S, there should be at least fourbit-clock cycles between the enabling of the transmit or receive section and the risingedge of the corresponding frame sync signal. The transition of TFS or RFS should besynchronized with the rising edge of external clock signal, STCK or SRCK.Functional descriptionK51 Sub-Family Reference Manual, Rev. 6, Nov 20111474 Freescale Semiconductor, Inc.