NXP Semiconductors freescale K51 Series Reference Manual

11.4.6 Digital Filter Clock Register (PORTx_DFCR)Addresses: PORTA_DFCR is 4004_9000h base + C4h offset = 4004_90C4hPORTB_DFCR is 4004_A000h base + C4h offset = 4004_A0C4hPORTC_DFCR is 4004_B000h base + C4h offset = 4004_B0C4hPORTD_DFCR is 4004_C000h base + C4h offset = 4004_C0C4hPORTE_DFCR is 4004_D000h base + C4h offset = 4004_D0C4hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0CSWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PORTx_DFCR field descriptionsField Description31–1ReservedThis read-only field is reserved and always has the value zero.0CSClock SourceThe digital filter configuration is valid in all digital pin muxing modes. Configures the clock source for thedigital input filters. Changing the filter clock source should only be done after disabling all enabled digitalfilters.0 Digital Filters are clocked by the bus clock.1 Digital Filters are clocked by the 1 kHz LPO clock.11.4.7 Digital Filter Width Register (PORTx_DFWR)The digital filter configuration is valid in all digital pin muxing modes.Addresses: PORTA_DFWR is 4004_9000h base + C8h offset = 4004_90C8hPORTB_DFWR is 4004_A000h base + C8h offset = 4004_A0C8hPORTC_DFWR is 4004_B000h base + C8h offset = 4004_B0C8hPORTD_DFWR is 4004_C000h base + C8h offset = 4004_C0C8hPORTE_DFWR is 4004_D000h base + C8h offset = 4004_D0C8hBit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0R 0FILTWReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Chapter 11 Port control and interrupts (PORT)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 251