NXP Semiconductors freescale K51 Series Reference Manual

SPIx_MCR field descriptions (continued)Field Description27FRZFreezeEnables the DSPI transfers to be stopped on the next frame boundary when the device enters Debugmode.0 Do not halt serial transfers in debug mode.1 Halt serial transfers in debug mode.26MTFEModified Timing Format EnableEnables a modified transfer format to be used.0 Modified SPI transfer format disabled.1 Modified SPI transfer format enabled.25PCSSEPeripheral Chip Select Strobe EnableEnables the PCS[5]/ PCSS to operate as a PCS Strobe output signal.0 PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal.1 PCS[5]/PCSS is used as an active-low PCS Strobe signal.24ROOEReceive FIFO Overflow Overwrite EnableIn the RX FIFO overflow condition, configures the DSPI to ignore the incoming serial data or overwriteexisting data. If the RX FIFO is full and new data is received, the data from the transfer, generating theoverflow, is ignored or shifted into the shift register.0 Incoming data is ignored.1 Incoming data is shifted into the shift register.23–22ReservedThis read-only field is reserved and always has the value zero.21–16PCSIS[5:0]Peripheral Chip Select x Inactive StateDetermines the inactive state of PCSx.0 The inactive state of PCSx is low.1 The inactive state of PCSx is high.15DOZEDoze EnableProvides support for an externally controlled Doze mode power-saving mechanism.0 Doze mode has no effect on DSPI.1 Doze mode disables DSPI.14MDISModule DisableAllows the clock to be stopped to the non-memory mapped logic in the DSPI effectively putting the DSPIin a software controlled power-saving state. The reset value of the MDIS bit is parameterized, with adefault reset value of "0".0 Enable DSPI clocks.1 Allow external logic to disable DSPI clocks.Table continues on the next page...Memory Map/Register DefinitionK51 Sub-Family Reference Manual, Rev. 6, Nov 20111134 Freescale Semiconductor, Inc.