48.3.17 UART FIFO Control Register (UARTx_CFIFO)This register provides the ability to program various control bits for FIFO operation. Thisregister may be read or written at any time. Note that writing the TXFLUSH andRXFLUSH bits may result in data loss and requires careful action to prevent unintended /unpredictable behavior, hence it is recommended that TE and RE be cleared prior toflushing the corresponding FIFO.Addresses: UART0_CFIFO is 4006_A000h base + 11h offset = 4006_A011hUART1_CFIFO is 4006_B000h base + 11h offset = 4006_B011hUART2_CFIFO is 4006_C000h base + 11h offset = 4006_C011hUART3_CFIFO is 4006_D000h base + 11h offset = 4006_D011hUART4_CFIFO is 400E_A000h base + 11h offset = 400E_A011hUART5_CFIFO is 400E_B000h base + 11h offset = 400E_B011hBit 7 6 5 4 3 2 1 0Read 0 0 0 TXOFE RXUFEWrite TXFLUSH RXFLUSHReset 0 0 0 0 0 0 0 0UARTx_CFIFO field descriptionsField Description7TXFLUSHTransmit FIFO/Buffer FlushWriting to this bit causes all data that is stored in the transmit FIFO/buffer to be flushed. This does notaffect data that is in the transmit shift register.0 No flush operation occurs.1 All data in the transmit FIFO/Buffer is cleared out.6RXFLUSHReceive FIFO/Buffer FlushWriting to this bit causes all data that is stored in the receive FIFO/buffer to be flushed. This does notaffect data that is in the receive shift register.0 No flush operation occurs.1 All data in the receive FIFO/buffer is cleared out.5–2ReservedThis read-only field is reserved and always has the value zero.1TXOFETransmit FIFO Overflow Interrupt EnableWhen this bit is set the TXOF flag will generate an interrupt to the host.0 TXOF flag does not generate an interrupt to the host.1 TXOF flag generates an interrupt to the host.0RXUFEReceive FIFO Underflow Interrupt EnableWhen this bit is set the RXUF flag will generate an interrupt to the host.Table continues on the next page...Chapter 48 Universal Asynchronous Receiver/Transmitter (UART)K51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 1245