NXP Semiconductors freescale K51 Series Reference Manual

7.5 Power modes shutdown sequencingWhen entering stop or other low-power modes, the clocks are shut off in an orderlysequence to safely place the chip in the targeted low-power state. All low-power entrysequences are initiated by the core executing an WFI instruction. The ARM core'soutputs, SLEEPDEEP and SLEEPING, trigger entry to the various low-power modes:• System level wait and VLPW modes equate to: SLEEPING & SLEEPDEEP• All other low power modes equate to: SLEEPING & SLEEPDEEPWhen entering the non-wait modes, the chip performs the following sequence:• Shuts off Core Clock and System Clock to the ARM Cortex-M4 core immediately.• Polls stop acknowledge indications from the non-core crossbar masters (DMA),supporting peripherals (SPI, PIT) and the Flash Controller for indications that SystemClocks, Bus Clock and/or Flash Clock need to be left enabled to complete apreviously initiated operation, effectively stalling entry to the targeted low powermode. When all acknowledges are detected, System Clock, Bus Clock and FlashClock are turned off at the same time.• MCG and Mode Controller shut off clock sources and/or the internal supplies drivenfrom the on-chip regulator as defined for the targeted low power mode.In wait modes, most of the system clocks are not affected by the low power mode entry.The Core Clock to the ARM Cortex-M4 core is shut off. Some modules support stop-in-wait functionality and have their clocks disabled under these configurations.The debugger modules support a transition from stop, wait, VLPS, and VLPW back to ahalted state when the debugger is enabled. This transition is initiated by setting the DebugRequest bit in MDM-AP control register. As part of this transition, system clocking is re-established and is equivalent to normal run/VLPR mode clocking configuration.7.6 Module Operation in Low Power ModesThe following table illustrates the functionality of each module while the chip is in eachof the low power modes. (Debug modules are discussed separately; see Debug in LowPower Modes.) Number ratings (such as 2 MHz and 1 Mbps) represent the maximumfrequencies or maximum data rates per mode. Also, these terms are used:• FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if amodule does not have a limitation in its functionality, it is still listed as FF.• static = Module register states and associated memories are retained.Chapter 7 Power ManagementK51 Sub-Family Reference Manual, Rev. 6, Nov 2011Freescale Semiconductor, Inc. 197