NXP Semiconductors freescale K51 Series Reference Manual

Section Number Title PageChapter 36Voltage Reference (VREFV1)36.1 Introduction...................................................................................................................................................................82136.1.1 Overview......................................................................................................................................................82236.1.2 Features........................................................................................................................................................82236.1.3 Modes of Operation.....................................................................................................................................82336.1.4 VREF Signal Descriptions...........................................................................................................................82336.2 Memory Map and Register Definition..........................................................................................................................82336.2.1 VREF Trim Register (VREF_TRM)............................................................................................................82436.2.2 VREF Status and Control Register (VREF_SC)..........................................................................................82536.3 Functional Description..................................................................................................................................................82636.3.1 Voltage Reference Disabled, SC[VREFEN] = 0.........................................................................................82636.3.2 Voltage Reference Enabled, SC[VREFEN] = 1..........................................................................................82636.4 Initialization/Application Information..........................................................................................................................827Chapter 37Programmable Delay Block (PDB)37.1 Introduction...................................................................................................................................................................82937.1.1 Features........................................................................................................................................................82937.1.2 Implementation............................................................................................................................................83037.1.3 Back-to-back Acknowledgement Connections............................................................................................83137.1.4 DAC External Trigger Input Connections...................................................................................................83137.1.5 Block Diagram.............................................................................................................................................83137.1.6 Modes of Operation.....................................................................................................................................83337.2 PDB Signal Descriptions..............................................................................................................................................83337.3 Memory Map and Register Definition..........................................................................................................................83337.3.1 Status and Control Register (PDBx_SC).....................................................................................................83537.3.2 Modulus Register (PDBx_MOD).................................................................................................................83737.3.3 Counter Register (PDBx_CNT)...................................................................................................................83837.3.4 Interrupt Delay Register (PDBx_IDLY)......................................................................................................838K51 Sub-Family Reference Manual, Rev. 6, Nov 201130 Freescale Semiconductor, Inc.