NXP Semiconductors freescale K51 Series Reference Manual

48.4.2.7 Hardware flow controlTo support hardware flow control, the receiver can be programmed to automaticallydeassert and assert RTS.• RTS will remain asserted until the transfer is completed, even if the transmitter isdisabled mid way through a data transfer, see Transceiver driver enable using RTSfor more details.• If the receiver request-to-send functionality is enabled, the receiver automaticallydeasserts RTS if the number of characters in the receiver data register is equal to orgreater than receiver data buffer's watermark, RWFIFO[RXWATER].• The receiver asserts RTS when the number of characters in the receiver data registeris less than the watermark. It is not affected by whether RDRF is asserted.• Even if RTS is deasserted, the receiver continues to receive characters until thereceiver data buffer is full or is overrun.• If the receiver request-to-send functionality is disabled, the receiver RTS remainsdeasserted.The following figure shows receiver hardware flow control functional timing. Along withthe actual character itself, RXD shows the start bit. The stop bit also indicated, with adashed line if necessary. The watermark is set to 2.C1 C2 C3 C4RXDC3databufferreadS1[RDRF]RTS_BC1 in reception1C1 C3StatusRegister 1readC1 C2Figure 48-228. Receiver hardware flow control timing diagram48.4.2.8 Infrared decoderThe infrared decoder converts the received character from the IrDA format to the NRZformat used by the receiver. It also has a 16-RT clock counter that filters noise andindicates when a '1' is being received.Functional descriptionK51 Sub-Family Reference Manual, Rev. 6, Nov 20111274 Freescale Semiconductor, Inc.